PCI: tegra194: Fix Root Port interrupt handling

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[ Upstream commit 6646e99bce ]

As part of Root Port interrupt handling, level-0 register is read first and
based on the bits set in that, corresponding level-1 registers are read for
further interrupt processing. Since both these values are currently read
into the same 'val' variable, checking level-0 bits the second time around
is happening on the 'val' variable value of level-1 register contents
instead of freshly reading the level-0 value again.

Fix by using different variables to store level-0 and level-1 registers
contents.

Link: https://lore.kernel.org/r/20220721142052.25971-11-vidyas@nvidia.com
Fixes: 56e15a238d ("PCI: tegra: Add Tegra194 PCIe support")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Vidya Sagar 2022-07-21 19:50:46 +05:30 • committed by Greg Kroah-Hartman

parent 50bf45181c

commit ebe2d576ce

1 changed files with 22 additions and 24 deletions

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drivers/pci/controller/dwc/pcie-tegra194.c

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