arm64: Fix DMA range invalidation for cache line unaligned buffers

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If the buffer needing cache invalidation for inbound DMA does start or
end on a cache line aligned address, we need to use the non-destructive
clean&invalidate operation. This issue was introduced by commit
7363590d2c (arm64: Implement coherent DMA API based on swiotlb).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Jon Medhurst (Tixy) <tixy@linaro.org>

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Catalin Marinas 2014-04-01 18:32:55 +01:00

parent d253b4406d

commit ebf81a938d

1 changed files with 11 additions and 4 deletions

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arch/arm64/mm/cache.S

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