drm/msm/dpu: Describe TEAR interrupt registers for DSI interfaces

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All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of
the PINGPONG block and into the INTF block.  Wire up the IRQ register
masks in the interrupt table for enabling, reading and clearing them.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/534244/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-18-27ce1a5ab5c6@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

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Marijn Suijten 2023-04-27 00:37:32 +02:00 • committed by Dmitry Baryshkov

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commit ec6e9b673a

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28

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

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4

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h

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