RISC-V: Add initial StarFive JH7100 device tree

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Add initial device tree for the JH7100 RISC-V SoC by StarFive Ltd. This
is a test chip for their upcoming JH7110 SoC.

The CPU and cache data is based on the device tree in the vendor u-boot
port.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>

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Emil Renner Berthing 2021-10-10 16:48:27 +02:00

parent b0ad20a3b6

commit ec85362fb1

1 changed files with 230 additions and 0 deletions

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arch/riscv/boot/dts/starfive/jh7100.dtsi

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