clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock

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The A64 PLL_CPU clock has the same instability if some factor changed
without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,
H3.

Add the mux and pll notifiers for A64 CPU clock to workaround the
problem.

Fixes: c6a0637460 ("clk: sunxi-ng: Add A64 clocks")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>

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Icenowy Zheng 2020-01-03 22:35:03 -08:00 • committed by Maxime Ripard

parent b406cadbc8

commit ec97faff74

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drivers/clk/sunxi-ng/ccu-sun50i-a64.c

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