drm/amd/display: Temp disable repeater FGCG as workaround

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[why & how]
There is an issue that is seemingly limited to DCN42 where systems with
IOMMU enabled will hang during reboot stress testing. The hang happens shortly
after DCN PG exit happens and HUBP is programmed for the first flip, but before
the first surface address is latched. Testing has shown that disabling
DCCG_GLOBAL_FGCG_REP_DIS, HUBP_FGCG_REP_DIS, and DCFCLK_GATE_DIS can mask this
issue.

Disable FGCG for these three repeater bits to avoid issue while debug is on-going.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Ovidiu Bunea 2026-05-21 15:27:11 -04:00 • committed by Alex Deucher

parent 0fde96e06f

commit ec9b4b2629

5 changed files with 21 additions and 2 deletions

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1

drivers/gpu/drm/amd/display/dc/dc.h

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6

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

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6

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

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9

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

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1

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

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