From ecae06f3ef5328e1bf852eae9091c7e7b0dd7c76 Mon Sep 17 00:00:00 2001 From: Jesse Zhang Date: Mon, 21 Sep 2026 11:06:42 +0800 Subject: [PATCH] drm/amdgpu/mes11: read the gfx user queue VMID for MMIO reset Read the MES-assigned VMID from CP_GFX_HQD_VMID under srbm_mutex when resetting a GFX user queue over MMIO. Kernel queues keep the IB VMID supplied by the caller. Signed-off-by: Jesse Zhang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index cc691cd0aca0..cb750342b458 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -699,7 +699,8 @@ static int mes_v11_0_reset_compute_pipe_mmio(struct amdgpu_device *adev, static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, uint32_t me_id, uint32_t pipe_id, - uint32_t queue_id, uint32_t vmid) + uint32_t queue_id, uint32_t vmid, + bool is_kq) { struct amdgpu_device *adev = mes->adev; uint32_t value, reg; @@ -708,11 +709,15 @@ static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_typ amdgpu_gfx_rlc_enter_safe_mode(adev, 0); if (queue_type == AMDGPU_RING_TYPE_GFX) { - dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", - me_id, pipe_id, queue_id, vmid); - mutex_lock(&adev->gfx.reset_sem_mutex); gfx_v11_0_request_gfx_index_mutex(adev, true); + mutex_lock(&adev->srbm_mutex); + soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); + /* Userq VMIDs are assigned by MES; KGQ uses the supplied IB VMID. */ + if (!is_kq) { + value = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); + vmid = REG_GET_FIELD(value, CP_GFX_HQD_VMID, VMID); + } /* all se allow writes */ WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); @@ -722,6 +727,8 @@ static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_typ else value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); + soc21_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); gfx_v11_0_request_gfx_index_mutex(adev, false); mutex_unlock(&adev->gfx.reset_sem_mutex); @@ -1165,7 +1172,8 @@ static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, if (input->use_mmio) { int r = mes_v11_0_reset_queue_mmio(mes, input->queue_type, input->me_id, input->pipe_id, - input->queue_id, input->vmid); + input->queue_id, input->vmid, + input->is_kq); if (r) return mes_v11_0_reset_pipe_mmio(mes, input->queue_type, input->me_id, input->pipe_id,