ASoC: max98090: Correct pclk divisor settings

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The Baytrail-based chromebooks have a 20MHz mclk, the code was setting
the divisor incorrectly in this case.  According to the 98090
datasheet, the divisor should be set to DIV1 for 10 <= mclk <= 20.
Correct this and the surrounding clock ranges as well to match the
datasheet.

Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>

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Dylan Reid 2014-11-03 10:28:56 -08:00 • committed by Mark Brown

parent f114040e3e

commit ece509c109

1 changed files with 3 additions and 3 deletions

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sound/soc/codecs/max98090.c

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