dt-bindings: interrupt-controller: Add MIPS P8700 aclint-sswi

Browse source

Add ACLINT-SSWI variant for the MIPS P8700 SoC. This CPU has a SSWI device
compliant with the RISC-V draft spec (see [1]).

CPU indexes on this platform are not continuous, instead it uses bit-fields
to encode hart,core,cluster numbers, thus the DT property
"riscv,hart-indexes" is mandatory for it.

Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/all/20250612143911.3224046-4-vladimir.kondratiev@mobileye.com
Link: https://github.com/riscvarchive/riscv-aclint [1]

...

This commit is contained in:

Vladimir Kondratiev 2025-06-12 17:39:07 +03:00 • committed by Thomas Gleixner

parent 81f335e106

commit ed651979bb

1 changed files with 55 additions and 9 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

64

Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml

View file