crypto: arm64/aes-modes - get rid of literal load of addend vector

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Replace the literal load of the addend vector with a sequence that
performs each add individually. This sequence is only 2 instructions
longer than the original, and 2% faster on Cortex-A53.

This is an improvement by itself, but also works around a Clang issue,
whose integrated assembler does not implement the GNU ARM asm syntax
completely, and does not support the =literal notation for FP registers
(more info at https://bugs.llvm.org/show_bug.cgi?id=38642)

Cc: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

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Ard Biesheuvel 2018-08-23 17:48:45 +01:00 • committed by Herbert Xu

parent 00227e3a1d

commit ed6ed11830

1 changed files with 9 additions and 7 deletions

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arch/arm64/crypto/aes-modes.S

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