PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASK

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The value under PORT_LOGIC_LINK_WIDTH_MASK is 0x1, 0x2, 0x4, 0x8.  In IP
v4.2, bits [16:8] are defined for NUM_OF_LANES.  But in IP v4.4, bits[12:8]
are defined for NUM_OF_LANES, bits [16:13] are for other usages (bit 16 is
AUTO_LANE_FLIP_CTRL_EN, bits [15:13] are PRE_DET_LANE).

As there is no conflict about NUM_OF_LANES between v4.2 and v4.4, change
the mask value to avoid future problems.

Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>

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Zhou Wang 2015-08-26 11:17:34 +08:00 • committed by Bjorn Helgaas

parent 6ff33f3902

commit ed8b472df4

1 changed files with 1 additions and 1 deletions

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drivers/pci/host/pcie-designware.c

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