clk: tegra: Fixup post dividers on Tegra210

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Commit 86c679a522 ("clk: tegra: pll: Fix _pll_ramp_calc_pll logic and
_calc_dynamic_ramp_rate") changed the PLL divider computation logic to
consistently use P-divider values from tables as real dividers rather
than the hardware values. Unfortunately for some reason many of the
Tegra210 clocks didn't have their tables updated (most likely an over-
sight by me when applying the patches). This commit fixes them all up.

Cc: Jon Hunter <jonathanh@nvidia.com>
Cc: Rhyland Klein <rklein@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Thierry Reding 2016-02-05 17:17:32 +01:00

parent 1a695a905c

commit eddb65e7fd

1 changed files with 47 additions and 47 deletions

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drivers/clk/tegra/clk-tegra210.c

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