phy: cadence-torrent: Add PCIe + DP multilink configuration for 100MHz refclk

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Add multilink DP configuration support for 100MHz reference clock rate.
This is the only clock rate supported currently for multilink PHY
configurations. Also, add PCIe + DP multiprotocol multilink register
configuration sequences for 100MHz refclk with no SSC.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20230418173157.25607-4-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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Swapnil Jakhade 2023-04-18 19:31:56 +02:00 • committed by Vinod Koul

parent c756cc1621

commit ede775a87b

1 changed files with 227 additions and 57 deletions

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drivers/phy/cadence/phy-cadence-torrent.c

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