clk: sunxi: A31: Fix wrong AHB gate number

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According to the manual the gate clock for MMC3 is at bit 11, and NAND1
is controlled by bit 12.

Fix the gate bit definitions in the clock driver.

Fixes: c6e6c96d8f ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

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Andre Przywara 2019-01-23 00:59:11 +00:00 • committed by Maxime Ripard

parent 5c59801f70

commit ee0b27a3a4

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drivers/clk/sunxi-ng/ccu-sun6i-a31.c

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