KVM: x86: Sync SPTEs when injecting page/EPT fault into L1

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When injecting a page fault or EPT violation/misconfiguration, KVM is
not syncing any shadow PTEs associated with the faulting address,
including those in previous MMUs that are associated with L1's current
EPTP (in a nested EPT scenario), nor is it flushing any hardware TLB
entries.  All this is done by kvm_mmu_invalidate_gva.

Page faults that are either !PRESENT or RSVD are exempt from the flushing,
as the CPU is not allowed to cache such translations.

Signed-off-by: Junaid Shahid <junaids@google.com>
Co-developed-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Message-Id: <20200320212833.3507-8-sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

...

This commit is contained in:

Junaid Shahid 2020-03-20 14:28:03 -07:00 • committed by Paolo Bonzini

parent 0cd665bd20

commit ee1fa209f5

3 changed files with 17 additions and 8 deletions

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12

arch/x86/kvm/vmx/nested.c

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2

arch/x86/kvm/vmx/vmx.c

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11

arch/x86/kvm/x86.c

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