clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets

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Add support for the PLLVDO clock and its related CRU clocks and reset
entries in the r9a09g057 CPG driver. Introduce `CLK_PLLVDO` and associated
clocks like `CLK_PLLVDO_CRU0`, `CLK_PLLVDO_CRU1`, `CLK_PLLVDO_CRU2`, and
`CLK_PLLVDO_CRU3`, along with their corresponding dividers.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241202203916.48668-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Lad Prabhakar 2024-12-02 20:39:16 +00:00 • committed by Geert Uytterhoeven

parent 03108a2614

commit ee47b94102

2 changed files with 51 additions and 0 deletions

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45

drivers/clk/renesas/r9a09g057-cpg.c

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6

drivers/clk/renesas/rzv2h-cpg.h

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