clk: sunxi-ng: sun6i: Use sigma-delta modulation for audio PLL

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The audio blocks require specific clock rates. Until now we were using
the closest clock rate possible with integer N-M factors. This resulted
in audio playback being slightly slower than it should be.

The vendor kernel gets around this (for newer SoCs) by using sigma-delta
modulation to generate a fractional-N factor. As the PLL hardware is
identical in most chips, we can back port the settings from the newer
SoC, in this case the H3, onto the A31.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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Chen-Yu Tsai 2017-10-12 16:37:04 +08:00 • committed by Maxime Ripard

parent 042f7f8f97

commit ee6501d692

1 changed files with 25 additions and 13 deletions

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drivers/clk/sunxi-ng/ccu-sun6i-a31.c

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