drm/amd/display: Limit DCN32 8 channel or less parts to DPM1 for FPO

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- Due to hardware related QoS issues, we need to limit certain
  SKUs with less memory channels to DPM1 and above.
- At DPM0 + workload running, the urgent return latency can
  exceed 15us (the expected maximum is 4us) which results in underflow

Cc: stable@vger.kernel.org
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Saaem Rizvi <SyedSaaem.Rizvi@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Alvin Lee 2023-04-10 14:37:27 -04:00 • committed by Alex Deucher

parent 8f3589bb6f

commit ee7be8f3de

3 changed files with 19 additions and 0 deletions

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2

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

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15

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

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2

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

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