drm/i915/dg2: Implement WM0 cursor WA for DG2

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Bug in the register unit which results in WM1 register
used when only WM0 is enabled on cursor.
Software workaround is when only WM0 enabled on cursor,
copy contents of CUR_WM_0[30:0] (exclude the enable bit)
into CUR_WM_1[30:0].

v2:  - s/dev_priv/i915/ (Ville Syrjälä)
     - Removed unneeded brackets (Ville Syrjälä)

HSDES: 14012656716

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211118093907.18510-1-stanislav.lisovskiy@intel.com

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Stanislav Lisovskiy 2021-11-18 11:39:07 +02:00

parent 2052287a74

commit eeb04fa64a

1 changed files with 13 additions and 5 deletions

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18

drivers/gpu/drm/i915/intel_pm.c

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