clk: tegra: dpaux and dpaux1 are fixed factor clocks

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The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed
factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have
a gate bit in the peripheral clock registers.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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This commit is contained in:

Thierry Reding 2015-04-20 15:10:43 +02:00

parent 98c4b3661b

commit eede7113aa

3 changed files with 12 additions and 2 deletions

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2

drivers/clk/tegra/clk-tegra-periph.c

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4

drivers/clk/tegra/clk-tegra124.c

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8

drivers/clk/tegra/clk-tegra210.c

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