mmc: meson-gx: initialize sane clk default before clock register

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On boot, the clock divider value is 0 which is a weird unsupported value.
For example, accessing the cfg register with this value set would crash
the SoC.

Previous change removed 0 as possible value for CCF but forgot to properly
initialize the register before registering the clock. This leads to the
CCF finding an illegal value, which it complains about.

Initialize the register properly in a standalone patch so the fix can be
picked up if necessary. The change this fixed is: "mmc: meson-gx: remove
CLK_DIVIDER_ALLOW_ZERO clock flag".

Reported-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

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This commit is contained in:

Jerome Brunet 2017-08-28 16:29:03 +02:00 • committed by Ulf Hansson

parent 88411dea0f

commit ef5c48157e

1 changed files with 9 additions and 10 deletions

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drivers/mmc/host/meson-gx-mmc.c

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