clk: samsung: exynos7885: Correct "div4" clock parents

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"div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by
2 to achieve a by 4 division, thus their parents are the respective
"div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents.
This leads to the kernel thinking "div4"s and everything under them run
at 2x the clock speed. Fix this.

Fixes: 45bd8166a1 ("clk: samsung: Add initial Exynos7885 clock driver")
Signed-off-by: David Virag <virag.david003@gmail.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20221013151341.151208-1-virag.david003@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

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David Virag 2022-10-13 17:13:40 +02:00 • committed by Krzysztof Kozlowski

parent 9abf2313ad

commit ef80c95c29

1 changed files with 2 additions and 2 deletions

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drivers/clk/samsung/clk-exynos7885.c

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