drm/fsl-dcu: specify volatile registers

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Since we are using cached registers, we need to specify volatile
registers explicitly to avoid reading their value from the cache.
This allows to read the correct interrupt status in fsl_dcu_drm_irq
and clear the asserted bits only.

Signed-off-by: Stefan Agner <stefan@agner.ch>

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Stefan Agner 2015-11-17 18:05:25 -08:00

parent a36c9867d4

commit efb8b49196

1 changed files with 11 additions and 1 deletions

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drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c

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