cxgb4: Fix PCI-E Memory window interface for big-endian systems

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When doing reads and writes to adapter memory via the PCI-E Memory Window
interface, data gets swizzled on 4-byte boundaries on Big-Endian systems
because we need to account for the register read/write interface which
incorporates a swizzle onto the Little-Endian PCI-E Bus.

Based on original work by Casey Leedom <leedom@chelsio.com>

Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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Hariprasad Shenai 2015-02-25 16:50:04 +05:30 • committed by David S. Miller

parent 2b0c2e2d2a

commit f01aa633e0

2 changed files with 45 additions and 11 deletions

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2

drivers/net/ethernet/chelsio/cxgb4/cxgb4.h

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54

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

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