drm/amdgpu: Fix PCIe lane width calculation

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commit 41212e2fe7 upstream.

The calculation of the lane widths via ATOM_PPLIB_PCIE_LINK_WIDTH_MASK and
ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT macros did not increment the resulting
value, per the comment in pptable.h ("lanes - 1"), and per usage elsewhere.
Port of the radeon fix to amdgpu.

Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=102553
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

...

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Alex Deucher 2018-04-02 12:29:26 -05:00 • committed by Greg Kroah-Hartman

parent 57e5682661

commit f056e33397

1 changed files with 2 additions and 2 deletions

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drivers/gpu/drm/amd/amdgpu/si_dpm.c

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