ARM: 8661/1: dts: r7s72100: add l2 cache

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Note that early-bresp-disable and full-line-zero-disable are required
because the sideband signals between the CPU and L2C were not connected
in this SoC.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

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Chris Brandt 2017-02-16 18:55:55 +01:00 • committed by Russell King

parent a96bb19769

commit f08578e6da

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arch/arm/boot/dts/r7s72100.dtsi

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