ASoC: cs42l42: PLL must be running when changing MCLK_SRC_SEL

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Both SCLK and PLL clocks must be running to drive the glitch-free mux
behind MCLK_SRC_SEL and complete the switchover.

This patch moves the writing of MCLK_SRC_SEL to when the PLL is started
and stopped, so that it only transitions while the PLL is running.
The unconditional write MCLK_SRC_SEL=0 in cs42l42_mute_stream() is safe
because if the PLL is not running MCLK_SRC_SEL is already 0.

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Fixes: 43fc357199 ("ASoC: cs42l42: Set clock source for both ways of stream")
Link: https://lore.kernel.org/r/20210805161111.10410-1-rf@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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Richard Fitzgerald 2021-08-05 17:11:04 +01:00 • committed by Mark Brown

parent 8b353bbeae

commit f1040e86f8

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25

sound/soc/codecs/cs42l42.c

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1

sound/soc/codecs/cs42l42.h

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