OMAPDSS: HDMI: Modify logic to configure MCLK

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The MCLK mode defines a factor to divide the clock that is used to
generate the Audio Clock Regeneration packets, MCLK.

The divisor is not used when the CTS value is calculated by HW.
When the value is calculated by SW, it depends on the silicon
revision.

Signed-off-by: Ricardo Neri <ricardo.neri@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

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Ricardo Neri 2012-01-31 15:56:16 -06:00 • committed by Tomi Valkeinen

parent d8989d96eb

commit f15511e23d

1 changed files with 4 additions and 2 deletions

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drivers/video/omap2/dss/hdmi.c

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