clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register

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The current code defines W1 clock gate to be at 0x1cc, overlaying it
with the IR gate.

Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
causing interrupt floods on H6 (because interrupt flags can't be cleared,
due to IR module's bus being disabled).

Fixes: b7c7b05065 ("clk: sunxi-ng: add support for H6 PRCM CCU")
Signed-off-by: Ondrej Jirman <megous@megous.com>
Acked-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

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Ondrej Jirman 2019-06-04 17:40:36 +02:00 • committed by Maxime Ripard

parent fcdf445ff4

commit f167675486

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drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c

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