From f17ddf54f1e6700d5777e94574f3533cd5719661 Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Wed, 3 Jun 2026 22:29:37 -0400 Subject: [PATCH] drm/amdgpu: Temporarily Flush TLB on NPA mapping always This is a temporary patch to always flush TLBs when mapping NPA addresses. Signed-off-by: Mukul Joshi Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c index 695be1af295b..33d528af76c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c @@ -3713,12 +3713,8 @@ static inline u32 ualink_tlb_wb_offset(struct amdgpu_device *adev, u32 accel_id) static void amdgpu_ualink_flush_tlb(struct amdgpu_device *adev, u32 flush_type) { - uint64_t tlb_seq = amdgpu_vm_tlb_seq(&adev->ualink.npa_vm); u32 bit; - if (atomic64_xchg(&adev->ualink.last_flushed_tlb_seq, tlb_seq) == tlb_seq) - return; - bit = AMDGPU_MMHUB0_START; for_each_set_bit_from(bit, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)