From f1b63ded8bff1e6277a2b9f6e96c789ddcf90656 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Tue, 14 Jul 2026 10:11:20 +0530 Subject: [PATCH] arm64: dts: qcom: ipq8074: move PCIe phys and PERST# to port node To align with the newer style of binding, move the phys, PERST# to the port node. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260714-pcie_move_to_new_binding-v1-1-6bb25887a0dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 10 ++++++++-- arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 10 ++++++++-- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++-------- 3 files changed, 22 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index 5cf07caf4103..dea5ece600d4 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -54,12 +54,18 @@ &pcie0 { status = "okay"; - perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; +}; + +&pcie0_port0 { + reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; }; &pcie1 { status = "okay"; - perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; +}; + +&pcie1_port0 { + reset-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; }; &pcie_qmp0 { diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi index 34e2f80514a3..f5c125e20ada 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi @@ -40,12 +40,18 @@ &pcie0 { status = "okay"; - perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; +}; + +&pcie0_port0 { + reset-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; }; &pcie1 { status = "okay"; - perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; +}; + +&pcie1_port0 { + reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; }; &pcie_qmp0 { diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 256e12cf6d54..75a5ae30d966 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -841,9 +841,6 @@ #address-cells = <3>; #size-cells = <2>; - phys = <&pcie_qmp1>; - phy-names = "pciephy"; - ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */ @@ -902,11 +899,13 @@ "axi_m_sticky"; status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie_qmp1>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -929,9 +928,6 @@ #address-cells = <3>; #size-cells = <2>; - phys = <&pcie_qmp0>; - phy-names = "pciephy"; - ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */ @@ -993,11 +989,13 @@ "axi_s_sticky"; status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie_qmp0>; + #address-cells = <3>; #size-cells = <2>; ranges;