clk: renesas: r9a07g043: Add ethernet clock sources

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Ethernet reference clock can be sourced from PLL5_500 or PLL6. Add
support for ethernet source clock selection using SEL_PLL_6_2 mux.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402074626.25624-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Biju Das 2022-04-02 08:46:24 +01:00 • committed by Geert Uytterhoeven

parent 6c185664b3

commit f201eb8445

1 changed files with 13 additions and 0 deletions

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drivers/clk/renesas/r9a07g043-cpg.c

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