ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes

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This SoC is integrated with 4 Cortex-A9 cores.  The GIC bindings
document says that the bits[15:8] of the 3rd cell of the interrupts
property represents PPI interrupt CPU mask.  Because the timer
interrupts are wired to all of the 4 cores, bits[15:8] should be set
to 0xf.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

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Masahiro Yamada 2015-08-19 14:49:26 +09:00 • committed by Olof Johansson

parent 62060a3548

commit f2032f24c0

1 changed files with 2 additions and 2 deletions

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arch/arm/boot/dts/uniphier-proxstream2.dtsi

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