drm/i915/cdclk: Rewrite cdclk->voltage_level selection to use tables

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The cdclk->voltage_level if ladders are hard to read, especially as
they're written the other way around compared to how bspec lists
the limits. Let's rewrite them to use simple arrays that gives us
the max cdclk for each voltage level.

v2: Bump the jsl/ehl max cdclk in the table to 652.8 MHz to
    accommodate JSL machines in CI that boot with high cdclk

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231211221759.29725-1-ville.syrjala@linux.intel.com

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This commit is contained in:

Ville Syrjälä 2023-12-12 00:17:59 +02:00

parent e1a914aef2

commit f23fe4d7d7

1 changed files with 57 additions and 30 deletions

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drivers/gpu/drm/i915/display/intel_cdclk.c

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