drm/msm/a6xx: Fix PDC sleep sequence

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Since the PDC resides out of the GPU subsystem and cannot be reset in
case it enters bad state, utmost care must be taken to trigger the PDC
wake/sleep routines in the correct order.

The PDC wake sequence can be exercised only after a PDC sleep sequence.
Additionally, GMU firmware should initialize a few registers before the
KMD can trigger a PDC sleep sequence. So PDC sleep can't be done if the
GMU firmware has not initialized. Track these dependencies using a new
status variable and trigger PDC sleep/wake sequences appropriately.

Cc: stable@vger.kernel.org
Fixes: 4b565ca5a2 ("drm/msm: Add A6XX device support")
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673362/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

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Akhil P Oommen 2025-09-08 13:56:57 +05:30 • committed by Rob Clark

parent ea601501a0

commit f248d5d515

2 changed files with 23 additions and 11 deletions

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28

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

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6

drivers/gpu/drm/msm/adreno/a6xx_gmu.h

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