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MIPS: Loongson1B: Some fixes/updates for LS1B

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- Fix hanging ethernet issue of LS1B v2.0 by adding pbl field in plat data.
   (It seems that the MAC controller of LS1B v2.0 can only accept pbl=1)
 - Add GMAC1 support and setup MUX in terms of PHY mode.
 - Add CPUFreq support.
 - Add MUX Register Definitions.
 - Add PWM Register Definitions.
 - Update clock register bitfields according to the latest spec.
 - Update clock related stuff.

Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8024/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Kelvin Cheung 2014-10-10 11:40:01 +08:00 • committed by Ralf Baechle
commit f29ad10de6
9 changed files with 283 additions and 31 deletions
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