drm/i915: WaRsDisableCoarsePowerGating

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WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
disabled for platforms prior to BXT B0 and SKL GT3/GT4 till E0.

v2: Added GT3/GT4 Check.

Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Alex Dai <yu.dai@intel.com>
[danvet: Align continuation properly.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Sagar Arun Kamble 2015-09-12 10:17:51 +05:30 • committed by Daniel Vetter

parent 7a58bad0e6

commit f2d2fe9507

1 changed files with 7 additions and 4 deletions

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drivers/gpu/drm/i915/intel_pm.c

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