drm/nouveau/fifo/tu102: Turing channel preemption fix

Browse source

Previous hardware allowed a MMU fault to be generated by software to
trigger a context switch for engine recovery. Turing has the capability
to preempt all work from a specific runlist processor and removed the
registers currently used for triggering MMU faults. Attempting to access
these non-existent registers results in further errors, so use the
runlist preemption register instead.

Signed-off-by: Alistair Popple <apopple@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

...

This commit is contained in:

Alistair Popple 2020-10-30 13:36:45 +11:00 • committed by Ben Skeggs

parent 26a0cfc163

commit f2fcb0692d

1 changed files with 2 additions and 41 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

43

drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c

View file