drm/i915/d13: Add Wa_16015201720 disabling clock gating for PIPEDMC-A/B

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Add a workaround making sure that PIPEDMC-A/B is enabled when the
firmware needs these on D13 platforms to save/restore the registers
backed by the PW_1 and PW_A power wells.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220727164523.1621361-2-imre.deak@intel.com

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Imre Deak 2022-07-27 19:45:23 +03:00

parent fa6a4cdeaf

commit f31bccd398

2 changed files with 15 additions and 0 deletions

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8

drivers/gpu/drm/i915/display/intel_display_power.c

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7

drivers/gpu/drm/i915/i915_reg.h

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