dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S

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The driver will be modified (in the next commits) to be able to specify
individual power domain IDs for each IP.  The driver will still
support #power-domain-cells = <0>, thus, previous users are not
affected.

The #power-domain-cells = <1> has been instantiated only for RZ/G3S at
the moment, as individual platform clock drivers need to be adapted for
this to be supported on the rest of the SoCs.

Also, the description for #power-domain-cells is updated with links to
per-SoC power domain IDs.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/r/20240422105355.1622177-6-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Claudiu Beznea 2024-04-22 13:53:52 +03:00 • committed by Geert Uytterhoeven

parent 2d03ce9cd7

commit f33dca9ed6

1 changed files with 17 additions and 1 deletions

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Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

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