drm/exynos: exynos7_drm_decon: fix ideal_clk by converting it to Hz

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The clkdiv values are incorrect as ideal_clk is in kHz and the clock
rate of vclk is in Hz. Multiply 1000 to ideal_clk to bring it to Hz.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

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Kaustabh Chakraborty 2024-11-01 11:31:10 +09:00 • committed by Inki Dae

parent d31bbacf78

commit f3cb045e26

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drivers/gpu/drm/exynos/exynos7_drm_decon.c

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