clk: sunxi-ng: a523: add bus clock gates

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Add the various bus clock gates that control access to the devices'
register interface.
These clocks are each just one bit, typically the lower bits in some "BGR"
(Bus Gate / Reset) registers, for each device group: one for all UARTs,
one for all SPI interfaces, and so on.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307002628.10684-13-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

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Andre Przywara 2025-03-07 00:26:26 +00:00 • committed by Chen-Yu Tsai

parent 00bc60ea24

commit f3dabb29f0

1 changed files with 308 additions and 1 deletions

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drivers/clk/sunxi-ng/ccu-sun55i-a523.c

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