spi: cadence-quadspi: Add DTR support

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Double Transfer Rate (DTR) mode transfers data twice per clock cycle.
Add support for parsing DTR ops and set up the registers to allow it.

Most SPI NOR flashes expect 2 byte commands. Parse the 2-byte opcode
from SPI MEM and set it up in the CQSPI_REG_OP_EXT_LOWER register.

Increment the delay needed before issuing indirect writes because larger
delay is needed for DTR mode. With the current delay some writes end up
missing.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20201222184425.7028-8-p.yadav@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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Pratyush Yadav 2020-12-23 00:14:25 +05:30 • committed by Mark Brown

parent 0920a32cf6

commit f453f29397

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1 changed files with 242 additions and 39 deletions

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drivers/spi/spi-cadence-quadspi.c

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