riscv: andes: Support specifying symbolic firmware and hardware raw events

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Add the Andes AX45 JSON files that allows specifying symbolic event
names for the raw PMU events.

Signed-off-by: Locus Wei-Han Chen <locus84@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Ian Rogers <irogers@google.com>
Link: https://lore.kernel.org/r/20240222083946.3977135-11-peterlin@andestech.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

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Locus Wei-Han Chen 2024-02-22 16:39:46 +08:00 • committed by Palmer Dabbelt

parent 270fc77e7b

commit f5102e31c2

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68

tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json

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127

tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json

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57

tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json

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77

tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json

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1

tools/perf/pmu-events/arch/riscv/mapfile.csv

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1 # Format: 17 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core 18 0x5b7-0x0-0x0,v1,thead/c900-legacy,core 19 0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core 20 0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core