arm64: pmu: Wire-up Cortex A53 L2 cache events and DTLB refills

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Add missing L2 cache events: read/write accesses and misses, as well as
the DTLB refills.

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

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Florian Fainelli 2017-04-20 12:05:45 -07:00 • committed by Catalin Marinas

parent 24af6c4e4e

commit f5337346cd

1 changed files with 6 additions and 0 deletions

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arch/arm64/kernel/perf_event.c

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