drm/amd/display: check phy dpalt lane count config

Browse source

[Why]
Type-c PHY config is not align with dpcd lane count.
When those values didn't match, it cause driver do
link training with 4 lane but phy only can output 2 lane.
The link trainig always fail.

[How]
1. Modify get_max_link_cap function. According DPALT_DP4
to update max lane count.
2. Add dp_mst_verify_link_cap to handle MST case because
we didn't call dp_mst_verify_link_cap for MST case.

Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Lewis Huang 2019-09-05 15:33:58 +08:00 • committed by Alex Deucher

parent d832fc3b18

commit f537d474df

5 changed files with 26 additions and 1 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

3

drivers/gpu/drm/amd/display/dc/core/dc_link.c

View file

16

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

View file

1

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

View file

3

drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h

View file

4

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h

View file