dt-bindings: opp: qcom-nvmem: Support pstates provided by a power domain

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Some Qualcomm SoCs have support for Core Power Reduction (CPR).
On these platforms, we need to attach to the power domain provider
providing the performance states, so that the leaky device (the CPU)
can configure the performance states (which represent different
CPU clock frequencies).

Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

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Niklas Cassel 2019-08-30 12:29:15 +02:00 • committed by Viresh Kumar

parent a409906003

commit f6081a7309

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Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt

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