drm/i915: Fix FBC_FENCE_OFF

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Having a 4 byte register at 0x321b seems unlikely as that's not
4 byte aligned. Since later platforms have more or less the same FBC
registers with new names, assume that FBC_FENCE_OFF is at 0x3218 just
like DPFC_FENCE_YOFF.

This feels like a simple typo in BSpec. 321Bh looks a lot like 3218h
after all.

Should still be tested on real hardware of course. But I don't have
any mobile gen4 systems.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Ville Syrjälä 2014-01-23 16:49:17 +02:00 • committed by Daniel Vetter

parent 5cd5410e9a

commit f64f172659

1 changed files with 1 additions and 1 deletions

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drivers/gpu/drm/i915/i915_reg.h

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