x86, cacheinfo: Cleanup L3 cache index disable support

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Adaptions to the changes of the AMD northbridge caching code: instead
of a bool in each l3 struct, use a flag in amd_northbridges.flags to
indicate L3 cache index disable support; use a pointer to the whole
northbridge instead of the misc device in the l3 struct; simplify the
initialisation; dynamically generate sysfs attribute array.

Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com>
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>

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Hans Rosenfeld 2010-10-29 17:14:32 +02:00 • committed by Borislav Petkov

parent 9653a5c76c

commit f658bcfb26

3 changed files with 74 additions and 84 deletions

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1

arch/x86/include/asm/amd_nb.h

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10

arch/x86/kernel/amd_nb.c

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147

arch/x86/kernel/cpu/intel_cacheinfo.c

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