From f670603d372a6205a5ab26a678cf7792a14697b3 Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Tue, 8 Sep 2026 12:35:16 -0400 Subject: [PATCH] drm/amd/display: Enable double buffering for DSCCLK updates [Description] Double buffering needs to be enabled for DSCCLK updates otherwise a frame of underflow could occur when updating the DSC pipe config or DSC clock. Reviewed-by: Ilya Bakoulin Signed-off-by: Alvin Lee Signed-off-by: George Zhang Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h | 4 ++++ drivers/gpu/drm/amd/display/dc/dccg/dcn60/dcn60_dccg.c | 4 ++++ drivers/gpu/drm/amd/display/dc/dccg/dcn60/dcn60_dccg.h | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h index cecfb0a68030..f47733db96f7 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h @@ -256,6 +256,10 @@ type DSCCLK1_EN;\ type DSCCLK2_EN;\ type DSCCLK3_EN;\ + type DSCCLK0_DTO_DB_EN;\ + type DSCCLK1_DTO_DB_EN;\ + type DSCCLK2_DTO_DB_EN;\ + type DSCCLK3_DTO_DB_EN;\ type DISPCLK_DCCG_GATE_DISABLE;\ type DCCG_GLOBAL_FGCG_REP_DIS; \ type PHYASYMCLK_EN;\ diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn60/dcn60_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn60/dcn60_dccg.c index e08a9679aaf7..9f15e6adc715 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn60/dcn60_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn60/dcn60_dccg.c @@ -76,6 +76,7 @@ static void dccg60_set_dto_dscclk(struct dccg *dccg, uint32_t inst, switch (inst) { case 0: + REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_DTO_DB_EN, 1); REG_UPDATE_2(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, 1, DSCCLK0_DTO_MODULO, 1); REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 1); @@ -92,6 +93,7 @@ static void dccg60_set_dto_dscclk(struct dccg *dccg, uint32_t inst, break; case 1: + REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_DTO_DB_EN, 1); REG_UPDATE_2(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, 1, DSCCLK1_DTO_MODULO, 1); REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 1); @@ -103,6 +105,7 @@ static void dccg60_set_dto_dscclk(struct dccg *dccg, uint32_t inst, break; case 2: + REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_DTO_DB_EN, 1); REG_UPDATE_2(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, 1, DSCCLK2_DTO_MODULO, 1); REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 1); @@ -114,6 +117,7 @@ static void dccg60_set_dto_dscclk(struct dccg *dccg, uint32_t inst, break; case 3: + REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_DTO_DB_EN, 1); REG_UPDATE_2(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_PHASE, 1, DSCCLK3_DTO_MODULO, 1); REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, 1); diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn60/dcn60_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn60/dcn60_dccg.h index 3f068ccfcdd5..3a6b65dee154 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn60/dcn60_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn60/dcn60_dccg.h @@ -96,6 +96,10 @@ DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_EN, mask_sh),\ DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_EN, mask_sh),\ DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK3_EN, mask_sh),\ + DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_DTO_DB_EN, mask_sh),\ + DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_DTO_DB_EN, mask_sh),\ + DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_DTO_DB_EN, mask_sh),\ + DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK3_DTO_DB_EN, mask_sh),\ DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, mask_sh),\ DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_MODULO, mask_sh),\ DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, mask_sh),\